AccelChip's New IP-Explorer Technology Takes DSP Algorithm Optimization to New Heights
MILPITAS, Calif.—(BUSINESS WIRE)—Oct. 10, 2005—
AccelChip Inc., the industry's leading provider of
semiconductor Intellectual Property (IP) and software for MATLAB(R)
and Simulink(R) DSP algorithms targeting silicon, today announced new
technology that provides unparalleled automation for DSP applications
in FPGAs and ASICs. Extending the company's leadership in Model-Based
Design solutions, AccelChip(R) DSP Synthesis 2005.4 with
IP-Explorer(TM) Technology is available immediately.
Implementing DSP algorithms in silicon requires careful selection
of IP blocks based on their specifications in the context of the
target application. Prior to IP-Explorer designers were required to
have extensive knowledge about the blocks' characteristics across a
wide range of system parameters and silicon choices. Combining
IP-Explorer Technology with AccelChip DSP Synthesis software automates
and extends upward the design space exploration process to accommodate
macro-architectures, or functional variants of mathematical building
blocks such as sine, log, and divide functions. With the new
technology, AccelChip's DSP Synthesis automatically selects and
inserts the optimal AccelWare DSP IP implementation for each function
in the design based on system requirements such as frequency,
throughput, bit-width, area and sample-rate.
"AccelChip has always been unique in that we enable customers to
code and explore architectures at the macro-level for functions like
FFT, filters and trig functions using our AccelWare generators," said
Michael Bohm, AccelChip's CTO and vice president of product
development. "On the other hand, C-based tools only allow trade-offs
to be made at the micro-architecture level or multiplier and adder
level. AccelChip's new IP Explorer Technology has taken the
trial-and-error out of using IP blocks by enabling the tool to select
from various macro-architectures depending on specific design and
system requirements."
AccelChip is delivering on the promise of architectural synthesis.
For example, with IP-Explorer Technology, when an algorithm uses a
sine function, the tool chooses between CORDIC, linear-interpolated
look-up table, and bipartite table implementations, and selects the
appropriate bit widths based on the floating-point model. It then even
automatically inserts pipeline registers when needed to hit the
performance and area goals. Combining IP optimization and
architectural synthesis is an entirely new level of automation. The
IP-Explorer Technology will save customers tremendous time and
considerable effort getting complex DSP designs to market.
IP-Explorer utilizes extensive heuristic modeling based on over
6000 AccelChip and customer designs. AccelChip's automated IP
development system runs all possible combinations of AccelWare against
these designs using the latest versions of the most popular design
tools to determine silicon results. The resulting database is used by
IP-Explorer to select the optimal macro-architecture as a starting
point for the design. If system requirements change during product
development, the design is automatically updated to new architectures
if required. IP- Explorer Technology has been added to the AccelWare
Building Block Toolkit, supporting trigonometric, logarithmic and
division functions. Heuristic modeling will be added to the AccelWare
Signal Processing, Communications and Advanced Math Toolkits in
upcoming releases.
"AccelChip's MATLAB-based synthesis solution extends Xilinx's
Simulink-based tool, System Generator for DSP, by automating the
selection of models and their parameters for algorithms written in
MATLAB," said Omid Tahernia, vice president and general manager,
Xilinx DSP Division. "Our mutual customers are using this combination
of Model-Based Design solutions to accelerate the design of radar,
sonar, GPS and wireless communication systems. By using IP-Explorer
Technology, designers can now create smaller, faster designs in less
time when targeting Xilinx FPGAs."
Pricing and Availability
Version 2005.4 of AccelChip DSP Synthesis with IP-Explorer and
AccelWare IP Generator Toolkits is now shipping. Current AccelChip
customers on support will receive the new release at no additional
fee. For more information on AccelChip DSP Synthesis and AccelWare IP
Toolkits, please email sales@accelchip.com.
About the Company
AccelChip Inc. is the industry's leading provider of semiconductor
IP and software for MATLAB and Simulink DSP algorithms targeting
silicon. The company develops and markets design tools, integrated
verification flows, and parametric IP toolkits that combine to
automate the development and implementation of DSP algorithms in FPGAs
and ASICs. AccelChip's proven solution integrates the domain-specific
DSP design environment (MATLAB and Simulink) with industry-standard
hardware design flows from Aldec, Altera, Cadence, Mentor Graphics,
Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000,
AccelChip is located in Milpitas, California, and has design centers
in Portland, Oregon, and Carlsbad, California. AccelChip's Web address
is www.accelchip.com. For more information, contact Wendy Truax at
503-351-0103 or by email at wendy@hipcom.com.
AccelChip and AccelWare are registered trademarks of AccelChip
Inc. All other trade names referenced are the service marks,
trademarks, or registered trademarks of their respective companies.
Contact:
AccelChip Inc.
Wendy Truax, 503-351-0103
Email Contact
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